At least some analog processors (e.g., quantum processors) provide a plurality of analog computation devices (e.g., qubits) which are controllably coupled to each other by couplers. Problems may be “embedded” on the processor for computation (e.g., by representing the problems as problem graphs where vertices and edges correspond to computation devices and couplers, respectively). The number of physical computation devices and couplers provided by the processor is often limited, which constrains the size (in terms of vertices) and connectivity (in terms of edges) of problem graphs which may be conveniently embedded on the analog processor.
This constraint is a significant driver in the ongoing effort to develop ever-larger (in terms of computing devices) and more connected (in terms of couplers) analog processors. Such analog processors are generally capable of having larger and/or more connected problem graphs embedded on them and thus may be capable of solving a greater scope of problems. However, obtaining larger and/or more connected analog processors may involve substantial costs and/or may not even be possible at a particular time (e.g., because such a processor has yet to be designed or manufactured).
Other approaches can involve finding embeddings which more efficiently represent problems on the analog processor. For many combinations of problems and not-fully-connected processors, the process of embedding the problems on the processor involves some overhead in the form of requiring the use of additional computation devices and/or couplers. Some embedding algorithms may require less overhead than other embedding algorithms for a given processor/problem pair, and so finding appropriate embedding algorithms may expand the scope of problems which are representable on a given processor. However, such techniques are still bounded by the size and/or connectivity of the processor.
Examples of embedding techniques are provided in, for example, U.S. Pat. No. 7,984,012 and Discrete optimization using quantum annealing on sparse Ising models, Bian et al., Front. Phys., 18 Sep. 2014, DOI: 10.3389/fphy.2014.00056.
There is thus a general desire for systems and methods for expanding the set of problems which may be solved by a particular analog processor.
Some approaches employ interactions between an analog processor and a digital computing system. These approaches are described herein as hybrid approaches. For example, in an iterative method, an analog processor, such as a quantum computing system, may be designed, operated, and/or adapted to provide a rate of convergence that is greater than the rate of convergence of a digital computing system.
Examples of hybrid approaches are provided in, for example, US Patent Application Publication No. 2014-0337612 entitled Systems and Methods for Interacting with a Quantum Computing System.
The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.